1. Field of the Invention
The invention relates to the field of metal-oxide-silicon (MOS) memories.
2. Prior Art
Numerous integrated circuits fabricated utilizing metal-oxide-silicon (MOS) technology such as random-access memories (RAM) and the like are known in the prior art. Typically the MOS circuits must interface with other components such as ECL or TTL circuitry. In interfacing with TTL circuitry or logic, the swing of the TTL signal is not directly compatible with most MOS circuitry. Many circuits are known for making a TTL signal compatible with MOS circuitry, however, most of such circuits are inefficient and consume relatively large amounts of power. In some cases, particularly for clock driving circuits in memories a TTL/MOS buffer is deployed on a separate substrate for interfacing the MOS memory with the TTL circuit.
As will be seen, the improved MOS-RAM circuitry disclosed in this application includes a unique buffer which may be used for producing a high-level clock signal, or the like, in response to an input TTL signal. The buffer is both efficient and effective, and unlike prior art circuits does not require a large pull-down device to discharge the high-level line.
Bistable MOS sense amplifiers for sensing the discharging or charging of a line in an MOS memory array are commonly utilized. Often, particularly in dynamic memories, the loads of the bistable circuits are clocked to prevent the amplifier from dissipating power when not in use. Some prior art sense amplifiers also include a gating or common transistor coupled in series with both legs of the amplifier for selectively controlling current flow in both legs of the sense amplifier. lt has been recognized in the prior art that if this latter transistor is allowed to conduct prior to the time that the loads of the sense amplifier conduct the sensitivity of the amplifier is increased. This increased sensitivity is due in part to the large loads caused by the non-conducting amplified loads. In some circuits, two generators have been used to cause the loads to be activated subsequent to the activation of the common transistor. As is apparent, care must be taken to assure proper timing between the activation of the loads and common transistor.
The present invention provides the advantage gained with two generators for sequentially activating the load transistors and common transistor, however, with a single generator. A perturbation or hesitation in the driving signal for the sense amplifier, which is coupled to both the loads and common transistor, provides the same desired result obtained in the prior art.